141 p4c1024 p4c1024 high speed 128k x 8 cmos static ram the p4c1024 device provides asynchronous opera- tions with matching access and cycle times. memory locations are specified on address pins a 0 to a 16 . read- ing is accomplished by device selection ( ce 1 low and ce 2 high) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce 1 or oe is high or we or ce 2 is low. package options for the p4c1024 include 32-pin 300 mil dip and soj packages as well as 400 mil soj. the p4c1024 is a 1,048,576-bit high-speed cmos static ram organized as 128kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v 10% tolerance power supply. access times of 15 nanoseconds permit greatly en- hanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1024 is a member of a family of pace ram? products offer- ing fast access times. three-state outputs fully ttl compatible inputs and outputs advanced cmos technology fast t oe automatic power down packages 32-pin 300 mil dip and soj 32-pin 400 mil soj high speed (equal access and cycle times) 15/17/20/25/35 ns (commercial) 20/25/35/45 ns (industrial) single 5 volts 10% power supply easy memory expansion using ce ce ce ce ce 1, ce 2 and oe oe oe oe oe inputs common data i/o functional block diagram pin configuration
142 p4c1024
143 p4c1024 max capacitances (v cc = 5.0v, t a = 25 c, f = 1.0 mhz) symbol parameter test conditions max unit c in c out input capacitance output capacitance v in = 0v v out = 0v 8 10 pf pf symbol parameter min unit t rc 15 ns t aa address access time t ac chip enable access time t oh output hold from address change ns t lz chip enable to output in low z ns t hz chip disable to output in high z ns t oe output enable low to data valid ns t olz output enable low to low z ns t ohz output enable high to high z t pu chip enable to power up time ns t pd chip disable to power down time ns read cycle time 3 3 0 0 15 15 8 6 12 6 -15 min 17 3 3 0 0 max -17 17 17 9 7 7 15 -20 min max 3 3 0 0 20 20 9 9 9 20 -25 min 25 3 3 0 0 max 25 25 11 10 11 20 min -35 3 3 0 0 max 35 35 15 15 15 20 min -45 45 3 3 0 0 max 20 20 25 45 45 ns ns ns 20 20 35 ac electrical characteristics - read cycle (over recommended operating temperature & supply voltage) * tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. the device is continuously enabled for writing, i.e., ce 2 3 v ih (min), ce 1 , and we v il (max). switching inputs are 0v and 3v. power dissipation characteristics vs. speed symbol parameter unit i cc dynamic operating current commercial industrial 190 n/a 180 n/a ma ma -15 -17 temperature range -20 160 175 -25 150 165 -35 145 160 -45 n/a 155
144 p4c1024
145 p4c1024 notes: 6. ce 1 and we are low and ce 2 is high for write cycle. 7. oe is low for this write cycle to show twz and tow. 8. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in a high impedance state. 9. write cycle time is measured from the last valid address to the first transitioning address. write cycle no. 1 ( we we we we we controlled) (6) address ce 1 t wc data valid high impedance we data in data out data undefined (9) (4) t cw t aw t wp t dw t ah t dh t ow t as t wz (4,7) (7) ce 2 symbol parameter max min t wc t cw t as t wp t ah t dh t wz t ow write cycle time chip enable time to end of write address valid to end of write address set-up time write pulse width address hold time data valid to end of write data hold time write enable to output in high z output active from end of write ns t aw t dw -15 15 12 12 0 12 0 7 0 3 8 -17 min 17 13 13 0 12 0 7 0 3 max 8 -20 20 15 15 0 15 0 8 0 3 max min 10 -25 min 25 18 20 0 18 0 10 0 3 max 11 -35 min 35 22 25 0 22 0 15 0 3 max 15 -45 min 45 30 35 0 25 0 20 0 3 max 18 unit ns ns ns ns ns ns ns ns ns ac characteristics - write cycle (over recommended operating temperature & supply voltage)
146 p4c1024
147 p4c1024 p3 j3 j4 package suffix plastic dip, 300 mil wide standard plastic soj, 300 mil wide standard plastic soj, 400 mil wide standard description package suffix temperature range suffix temperature range suffix description c i commercial temperature range, 0?c to +70?c industrial temperature range, -40?c to +85?c ordering information performance semiconductor's part numbering scheme is as follows: selection guide the p4c1024 is available in the following temperature, speed and package options. n/a n/a n/a speed (ns) -20p3c -20j3c -20j4c -17 temperature range package commercial temperature plastic dip 300 plastic soj 300 plastic soj 400 industrial temperature plastic dip 300 plastic soj 300 plastic soj 400 -15 -15p3c -15j3c -15j4c -17p3c -17j3c -17j4c n/a n/a n/a -20 -20p3i -20j3i -20j4i -25 -25p3i -25j3i -25j4i -35 -35p3c -35j3c -35j4c -35p3i -35j3i -35j4i -25p3c -25j3c -25j4c n/a = not available 1024 p4c ss p t temperature range: c, i package code: p3, j3, j4 speed (access/cycle time): 15, 17, etc. device number: 1024 static ram prefix
148 p4c1024
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